Comlink of a PTVD - SHAM System

Abstract —– This paper focuses on super helical memory system’s design, ‘Engineering, Architectural and Satellite Communications’ as a theoretical approach of an invention-model to ‘store time-data’ in terms of anticipating the best memory location ever for data/time. The current release entails three concepts: 1the in-depth theoretical physics engineering of the chip, including its, 2architectural concept based on very large scale integration (VLSI) methods, and 3the time-data versus data-time algorithm. The ‘Parallel Time Varying & Data Super-helical Access Memory’ (PTVDSHAM), possesses a waterfall effect in its architecture dealing with the process of potential-difference output-switch into diverse logic and quantum states described as ‘Boolean logic & image-logic’, respectively. Quantum dot computational methods are explained by utilizing coiled carbon nanotubes (CCNTs) and carbon nanotube field effect transistors (CNFETs) in the chip’s architecture. Quantum confinement, categorized quantum well substrate, and B-field flux involvements are discussed in theory. Multi-access of coherent sequences of ‘qubit addressing’ in any magnitude, gained as pre-defined, here e.g., the ‘big O notation’ asymptotically confined into singularity while possessing a magnitude of ∞ for the orientation of array displacement. Gaussian curvature of k < 0 versus k′ > (k < 0) is debated in aim of specifying the 2D electron gas characteristics, data storage system for defining short and long time cycles for different CCNT diameters where space-time continuum is folded by chance for the particle. Precise pre/post-data timing for, e.g., seismic waves before earthquake mantle-reach event occurrence, including time varying self-clocking devices in diverse geographic locations for radar systems is given in the corresponding Subsections of the paper. This application could also be optional for data depository versus extraction in the best supercomputer system’s locations, autonomously. The theoretical fabrication process, electromigration between chip’s components is discussed as well.